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X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 1.0 * Features 2.0 Description Triple phase-locked loop (PLL) device provides exact ratiometric derivation of Audio, Processor, and Utility Clocks On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning Serial interface for Audio and Utility Clock frequency selection Board-programmable Processor Clock frequency selection Supports 32, 44.1, and 48kHz 256x oversampled DACs as well as 384x at 44.1kHz and 512x at 48kHz Tunable Audio Clock frequencies for undetectable resynchronization of audio and video streams Small circuit board footprint (16-pin 0.150 SOIC) Custom frequency selections available - contact your local AMI Sales Representative for more information * * * * * * * The FS6011-02 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6011-02 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator (nominally 27MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. Three high-resolution phase-locked loops independently generate three other selectable frequencies derived from the VCXO frequency. These clock frequencies are related to the VCXO frequency and to each other by exact ratios. The locking of all the output frequencies together can eliminate unpredictable artifacts in video systems and unpredictable electromagnetic interference (EMI) performance due to frequency harmonic stacking. Figure 1: Block Diagram PSEL0 PSEL1 Processor Clock PLL PCLK Figure 2: Pin Configuration SCLK SDATA 1 2 3 16 15 14 CLK27 ACLK VDD UCLK PCLK VSS PSEL0 PSEL1 XTUNE XIN VCXO XOUT Audio Clock PLL ACLK SLOAD VSS XIN FS6011 4 5 6 7 8 13 12 11 10 9 Utility Clock PLL UCLK XOUT XTUNE SLOAD SCLK SDATA CLK_27 Serial Interface VDD FS6011 16-pin (0.150) SOIC American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ,62 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TYPE DI DI DI P AI AO AI P DID DID P DO DO P DO DO NAME SCLK SDATA SLOAD VSS XIN XOUT XTUNE VDD PSEL1 PSEL0 VSS PCLK UCLK VDD ACLK CLK27 Serial Data Clock Serial Data Input Serial Port Load Ground VCXO Feedback VCXO Drive VCXO Tune Power Supply (+5V) PCLK Select MSB PCLK Select LSB Ground Processor Clock Output Utility Clock Output Power Supply (+5V) Audio Clock Output Reference Clock Output DESCRIPTION 3.0 3.1 Functional Block Description Phase-Locked Loops 3.3 Digital Interface Each of the three on-chip PLLs in the FS6011 multiplies the reference frequency to the desired frequency by a ratio of integers. This frequency multiplication is exact. 3.2 Output Tristate Control All four clock outputs of the FS6011 may be tristated to facilitate circuit board testing. To place the outputs in tristate mode, follow this sequence: 1. force XIN low (i.e. ground) 2. apply power to the device 3. wait until the internal power-on reset has deasserted 4. apply a negative-going transition to the PSEL0 pin Outputs may be re-enabled by removing and reapplying power to the FS6011. To re-enable outputs without removing power, apply a rising edge transition to the XIN in and follow it with a falling edge transition on the PSEL0 pin. Digital data is placed on the SDATA pin and clocked into the FS6011 internal shift register (D[0] first) with a rising edge on the SCLK pin. The shift register data is transferred to the FS6011 control registers with a rising edge on the SLOAD pin. Fifteen bits must be shifted into the internal registers before the parallel load can be performed. In addition to the normal control functions performed by D[13:0], there is one reserved bit, D[14], that should be set to zero. All control registers are initialized to zero on power-up. Figure 3: Communications Protocol tF tLO tHI tR SCLK thd:DAT tsu:DAT SDATA tsu:LD thd:LD tLO tHI SLOAD ,62 2 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 3.4 Voltage-Controlled Crystal Oscillator (VCXO) 4.0 Programming Information The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6011 system components. Loading capacitance for the crystal is internal to the FS6011. No external components (other than the resonator itself) are required for operation of the VCXO. The resonator loading capacitance is adjustable under register control. This permits factory coarse tuning of inexpensive resonators to the necessary precision for digital video applications. Refer to Section 4.6. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF nominal. The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to obtain the warping capability of a crystal oscillator is: Table 2: Register Summary BIT D[x] 0 1 2 REGISTER BIT DESCRIPTION ACLK Select (LSB) ACLK Select ACLK Select (MSB) ACLK Off-Speed Mode 3 Bit = 0 Bit = 1 Disable Off-Speed Mode Enable Off-Speed Mode ACLK Speed Control 4 Bit = 0 Bit = 1 5 6 7 Low Speed High Speed UCLK Select (LSB) UCLK Select UCLK Select (MSB) CLK27 Select 8 Bit = 0 Bit = 1 Selects VCXO Frequency Selects UCLK Frequency 9 10 11 12 Crystal Oscillator Coarse Tune (LSB) Crystal Oscillator Coarse Tune Crystal Oscillator Coarse Tune Crystal Oscillator Coarse Tune (MSB) VCXO Enable/Disable Control 13 Bit = 0 Bit = 1 Disable VCXO Mode Enable VCXO Mode f ( ppm) = 6 C1 x (C L 2 - C L1)x 10 2 x (C 0 + C L 2 )x (C 0 + C L1) 14 Reserved (should be set to 0) where CL1 and CL2 are the two extremes of the applied load capacitance. A crystal with the following parameters is used. With C1 = 0.02pF, C0 = 5pF, CL1 = 10pF, and CL2 = 22.66pF, the coarse tuning range is f = 0.02 x (22.66 - 10)x 10 6 = 305 ppm . 2 x (5 + 22.66 )x (5 + 10 ) ,62 3 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 4.1 Audio PLL Clock Frequencies (ACLK) 4.3 Utility PLL Clock Frequencies (UCLK) The ACLK frequency is controlled by register bits D[0], D[1], and D[2] accessed via the serial interface. The ACLK frequencies listed below are derived via the PLL Divider Ratio from a reference frequency of 27MHz. The UCLK frequency is controlled by register bits D[5], D[6] and D[7], accessed via the serial interface. UCLK frequencies listed below are derived via the PLL Divider Ratio from a reference frequency of 27MHz. Table 3: ACLK Frequency Select D[2] 0 0 0 0 1 1 1 1 D[1] 0 0 1 1 0 0 1 1 D[0] 0 1 0 1 0 1 0 1 PLL DIVIDER AUDIO RATIO OVERSAMPLING 1024 / 2250 1024 / 3375 1024 / 4500 1024 / 6750 1568 / 3750 1568 / 2500 1568 / 7500 1024 / 1125 48kHz x 256 32kHz x 256 48kHz x 256 / 2 32kHz x 256 / 2 44.1kHz x 256 44.1kHz x 384 44.1kHz x 256 / 2 48kHz x 512 ACLK (MHz) 12.288 8.192 6.144 4.096 11.2896 16.9344 5.6448 24.576 Table 5: UCLK Frequency Select D[7] 0 0 0 0 1 1 1 1 D[6] 0 0 1 1 0 0 1 1 D[5] 0 1 0 1 0 1 0 1 PLL DIVIDER RATIO 16 / 27 35 / 33 1568 / 3750 1 544 / 375 728 / 375 10 / 9 1024 / 1125 UCLK (MHz) 16.0000 28.6363 11.2896 27.0000 39.1680 52.4160 30.0000 24.5760 NOTE: Contact AMI for custom PLL frequencies NOTE: Contact AMI for custom PLL frequencies 4.2 Audio Clock Off-Speed Frequencies The ACLK frequencies shown may be smoothly modified to a slightly higher or lower value under register control. Register bit D[3] must be a logic-one to activate this mode. The value of D[4] controls whether the frequency will be adjusted slightly low (D[4] = 0) or high (D[4] = 1). 4.4 Processor PLL Frequencies (PCLK) The PCLK frequency is controlled by the logic levels on the PSEL0 and PSEL1 inputs. These inputs have weak pull-downs. PCLK frequencies listed below are derived via the PLL Divider Ratio from a reference frequency of 27MHz. Table 4: Audio Off Speed Frequencies D[4] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D[3] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PLL DIVIDER RATIO 1023 / 2250 1023 / 3375 1023 / 4500 1023 / 6750 1567 / 3750 1567 / 2500 1567 / 7500 1023 / 1125 1025 / 2250 1025 / 3375 1025 / 4500 1025 / 6750 1569 / 3750 1569 / 2500 1569 / 7500 1025 / 1125 ACLK (MHz) 12.276 8.184 6.138 4.092 11.2824 16.9236 5.6412 24.5520 12.3000 8.2000 6.1500 4.1000 11.2968 16.9432 5.6484 24.6000 Table 6: PCLK Frequency Select PSEL1 0 0 1 1 PSEL0 0 1 0 1 PLL DIVIDER RATIO 32 / 27 40 / 27 50 / 27 60 / 41 PCLK (MHz) 32.0000 40.0000 50.0000 39.5122 NOTE: Contact AMI for custom PLL frequencies ,62 4 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 4.5 Reference Frequencies (CLK27) The CLK27 output frequency is controlled by register bit D[8] that selects either the VCXO reference frequency or the UCLK frequency. Table 7: CLK27 Frequency Select D[8] 0 1 CLK27 Output VCXO Frequency UCLK Frequency Figure 4 shows the typical effect of the coarse and fine tuning mechanisms. The difference in VCXO frequency in parts-per-million (ppm) is shown as the fine tuning voltage on the XTUNE pin varies from 0V to 5V. The coarse tune range as shown is about 350ppm. As the crystal load capacitance is increased (with increasing Coarse Tune setting) the frequency is pulled somewhat less with each coarse step and the fine tuning range decreases. The fine tuning range always overlaps a few coarse tuning ranges, eliminating the possibility of holes in the VCXO response. Note that different crystal warping characteristics will change the scaling on the Y-axis, but not the overall characteristic of the curves. 4.6 VCXO Coarse Tuning and Enable VCXO Range (ppm) The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via D[12:9]. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled by setting D[13] to a logic-one or disabled by clearing the bit to a logic-zero. Figure 4: VCXO Coarse and Fine Tuning VCXO Range (ppm) vs. XTUNE Voltage (V) 200 150 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Coarse Tune Setting D[11:14] XTUNE Voltage = 0.0V XTUNE Voltage = 5.0V Table 8: VCXO Tuning Capacitance D[12] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D[11] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D[10] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D[9] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCXO TUNING CAPACITANCE (pF) 10.00 10.84 11.69 12.53 13.38 14.22 15.06 15.91 16.75 17.59 18.43 19.28 20.13 20.97 21.81 22.66 ,62 5 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 5.0 Electrical Specifications Table 9: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (human-body model) SYMBOL VDD VI VO IIK IOK TS TA TJ MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2 UNITS V V V mA mA C C C C kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 10: Operating Conditions PARAMETER Supply Voltage Ambient Operating Temperature Range Output Load Capacitance Crystal Resonator Frequency Crystal Resonator Motional Capacitance Serial Data Transfer Rate SYMBOL VDD TA CL fXIN CMOT AT cut 10 24 27 25 100 CONDITIONS/DESCRIPTION 5V 10% MIN. 4.5 0 TYP. 5 MAX. 5.5 70 15 28 UNITS V C pF MHz fF kb/s ,62 6 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 Table 11: DC Electrical Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS IDD fCLK = 27MHz; CL 50pF 58 80 mA Serial Communication Inputs (SCLK, SDATA, SLOAD) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current PCLK Select Inputs (PSEL0, PSEL1) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage * Input Leakage Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Drive (XOUT) High-Level Output Source Current * Low-Level Output Sink Current * VCXO Tuning Input (XTUNE) Input Leakage Current Clock Outputs (ACLK, CLK27, PCLK, UCLK) High-Level Output Source Current * Low-Level Output Sink Current * Output Impedance * Tristate Output Current Short Circuit Source Current * Short Circuit Sink Current * IOH IOL zOH zOL IOZ IOSH IOSL VO = 0V; shorted for 30s, max. VO = 5V; shorted for 30s, max. VO = 2.4V VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low -10 -60 65 -46 64 53 57 +10 mA mA A mA mA II -1 1 A IOH IOL VO = 0V; D[13] = 0 VO = 0V, V(XTUNE) = 5V; D[13] = 1 VO = 5V; D[13] = 0 VO = 5V, V(XTUNE) = 5V; D[13] = 1 -45 -52 53 63 mA mA VTH II CL(xtal) CL(XIN) As seen by an external crystal connected to XIN and XOUT; VCXO tuning disabled As seen by an external clock driver on XIN; XOUT unconnected; VCXO disabled -1 10 20 0.5VDD 1 V A pF pF VIH VIL IIH IIL VIH = 5V 2.4 VSS-0.3 5 -1 12.7 VDD+0.3 0.8 50 1 V V A A VIH VIL Vhys II -1 2.4 VSS-0.3 VDD+0.3 0.8 300 1 V V mV A ,62 7 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 Table 12: AC Timing Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER Clock Output (ACLK) SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS 12.288 8.192 6.144 48 48 48 48 47 48 48 47 740 760 730 710 650 570 680 730 370 270 190 140 470 680 240 770 52 52 52 52 52 52 52 51 Duty Cycle * From rising edge to rising edge at 2.5V 4.096 11.289 16.344 5.644 24.576 12.288 8.192 6.144 % Jitter, Absolute (long term) * tj(ab) Measured from rising edge to 1st rising edge after 0.1s at 2.5V; CL = 15pF, fREF = 27MHz 4.096 11.289 16.344 5.644 24.576 12.288 8.192 6.144 ps Jitter, Period * tj(P) Measured on the rising edges at 2.5V; CL = 15pF, fREF = 27MHz 4.096 11.289 16.344 5.644 24.576 ps Rise Time * Fall Time * Clock Stabilization Time * tr tf tSTB VO = 0.5V to 4.5V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF Output active from power-up 3.5 2.3 740 ns ns s ,62 8 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 Table 13: AC Timing Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER Clock Output (UCLK) SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS 16.000 28.636 11.289 48 48 48 44 43 42 48 48 580 620 780 2800 640 780 650 680 250 400 400 900 670 1500 790 680 52 52 52 48 47 46 52 52 Duty Cycle * From rising edge to rising edge at 2.5V 27.000 39.168 52.416 30.000 24.576 16.000 28.636 11.289 % Jitter, Absolute (long term) * tj(ab) Measured from rising edge to 1st rising edge after 0.1s at 2.5V; CL = 15pF, fREF = 27MHz 27.000 39.168 52.416 30.000 24.576 16.000 28.636 11.289 ps Jitter, Period * tj(P) Measured on the rising edges at 2.5V; CL = 15pF, fREF = 27MHz 27.000 39.168 52.416 30.000 24.576 ps Rise Time * Fall Time * Clock Stabilization Time * tr tf tSTB VO = 0.5V to 4.5V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF Output active from power-up 3.6 2.4 380 ns ns s ,62 9 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 Table 14: AC Timing Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER Clock Output (PCLK) SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS 32.000 48 48 48 48 410 620 630 620 430 460 530 670 52 52 52 52 Duty Cycle * From rising edge to rising edge at 2.5V 40.000 50.000 39.512 32.000 % Jitter, Absolute (long term) * tj(ab) Measured from rising edge to 1st rising edge after 0.1s at 2.5V; CL = 15pF, fREF = 27MHz 40.000 50.000 39.512 32.000 ps Jitter, Period * tj(P) Measured on the rising edges at 2.5V; CL = 15pF, fREF = 27MHz VO = 0.5V to 4.5V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF Output active from power-up 40.000 50.000 39.512 ps Rise Time * Fall Time * Clock Stabilization * Clock Output (CLK27) Duty Cycle * Clock Stabilization Time * Rise Time * Fall Time * tr tf tSTB 3.6 2.4 400 ns ns s Crystal oscillator frequency out, from rising edge to rising edge at 2.5V tSTB tr tf Output active from power-up VO = 0.5V to 4.5V; CL = 15pF VO = 4.5V to 0.5V; CL = 15pF 27 44 150 3.8 2.9 48 % s ns ns Table 15: Serial Interface Timing Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER SCLK clock frequency Set up time, load Hold time, load Set up time, data Hold time, data Rise time Fall time High time, serial clock Low time, serial clock SYMBOL fSCLK tsu:LD thd:LD tsu:DAT thd:DAT tr tf tH tL CONDITIONS/DESCRIPTION MIN. 0 MAX. 100 UNITS kHz s s ns s SLOAD SLOAD SDATA SDATA SDATA, SCLK SDATA, SCLK SCLK SCLK 4.7 4.0 250 0 1000 300 4.0 4.7 ns ns s s ,62 10 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 6.0 Package Information Table 16: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 0 MAX. 1.73 R 16 E H 0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89 8 1 AE"CAAC"#)#$E#AC ALL RADII: 0.005" TO 0.01" h x 45 7 typ. B e A2 D A1 SEATING PLANE 0.050 BSC 1.27 BSC A C L BASE PLANE Table 17: 16-pin SOIC (0.150") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL jA L11 L12 C11 CONDITIONS/DESCRIPTION Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS TYP. 108 4.0 3.0 0.4 0.5 UNITS C/W nH nH pF ,62 11 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 7.0 Ordering Information DEVICE NUMBER FS6011 FS6011 FONT PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 0C to 70C (Commercial) 0C to 70C (Commercial) SHIPPING CONFIGURATION Tube Tape-and-Reel ORDERING CODE 11228-003 11228-005 -02 -02 Copyright (c) 1998 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ,62 12 7.20.98 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 8.0 Demonstration Board A simple demonstration board and DOS-based software is available from American Microsystems that illustrates the capabilities of the FS6011. The board schematic is shown below. Components listed with an asterisk (*) are not required in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. A cabled interface between a computer parallel port (DB25 connector) and the board (J1) is provided. Contact your local sales representative or the company directly for more information. Figure 5: Board Schematic J1* 1 SCLK 2 SDATA 3 SLOAD 4 PSEL1 5 PSEL0 6 1 +5V +5V GND 3 +5V RP1 1k C6 12pF C7 12pF Y1 27MHz 4 5 6 7 +5V R6 10 8 C1 2.2F 2 R5* 100 C2 2.2F 16 15 14 13 12 11 10 9 R10* 47 UCLK R11* 47 PCLK R8* 47 CLK27 R9* 47 ACLK C4 0.1F R4* 100 R3* 100 R2* 100 C5* 100pF R7 10 +5V R1* 100 SCLK SDATA SLOAD VSS CLK27 ACLK VDD UCLK FS6011 XIN XOUT XTUNE VDD JP2 JP1 PCLK VSS PSEL0 PSEL1 C3 0.1F ,62 13 7.20.98 )6 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& X T July 1998 8.1 * * * * Contents Demonstration board Interface cable (DB25 to 6-pin connector) Data sheet Demonstration software, including: - - - INSTALL.BAT FS6011.BAT FS6011G.BAS 0.75kB 0.24kB 5.3kB 2. The following banner should appear: **************************************** * * * FS6011 Utility Program * * * * PRESS ANY KEY TO CONTINUE..... * * * **************************************** 3. After pressing any key, a menu should appear containing a list of the program hot keys, a message that the computer parallel (LPT1) port was found, and the address at which the port was found. *********************** * FS6011 Pgm. Utility * * * * chip (R)efresh * * chip (I)nitialize * * (A)clk = 0* * a(O)ffset = 0* * (C)lk27 = 0* * (U)clk = 0* * (V)cxo = 0* * vcxo (E)nable = 0 * * (P)clk = 0* * e(X)it * *********************** Refer to Table 18 for a description of each hot key. 4. To change the frequency of the desired clock, press the appropriate hot key. The keys are not case sensitive. 5. Refer (in the FS6011 data sheet) to Table 3 and Table 4 for ACLK frequencies, Table 5 for UCLK frequencies, and Table 6 for PCLK frequencies. 6. Observe the response to the hot key selection. Repeated pressing of the same key will scroll through the entire range of frequencies for the selected clock, returning to the initial frequency. 7. Pressing a hot key strobes a 15-bit message to the demo board via the interface cable. The response to the key selection is shown below: Writing... (0x000) Binary: LSB 000000000000000 MSB where the numbers are the data in hex and binary. Note that the PCLK frequency is changed by directly addressing pins 4 and 5 (PSEL0 and PSEL1) of the device. Therefore the hot key response message will be unchanged when selecting the (P)CLK hot key. Press X to exit the demo program. 14 7.20.98 8.2 * * * Requirements PC running MS-DOS or MS Windows 3.1x, with accessible parallel (LPT1) port MS-QBasic v. 1.1 or later (or equivalent software) 6.3kB available space on drive C: 8.3 Board Setup and Software Installation Instructions 1. At the appropriate disk drive prompt (A:\) type Install to automatically copy demo files to the C: drive. NOTE: This demo software requires Microsoft QBasic or equivalent to run. Make sure the directory containing qbasic.exe is in the DOS path statement, or move the demo files to a directory containing Basic. 2. Connect a +5 Volt power supply to the board: RED = +5V, BLACK = ground. 3. Remove all software keys from the computer parallel port. 4. Connect the supplied interface cable to the parallel port (DB25 connector) and to the demo board (6-pin connector). Make sure the cable is facing away from the board - pin 1 is the red wire. 5. Connect the clock outputs to the target application board with a twisted-pair cable. 8.4 Demo Program 1. Type FS6011 at the C:\FS6011 prompt to run the Qbasic-based demo program. ,62 X T 'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,& )6 July 1998 Table 18: Hot Key Description Command Refresh Initialize ACLK ACLK Offset UCLK CLK27 Hot Key R I A O U C 0-2 3-4 5-7 8 000-111 00-11 000-111 0-1 00001111 0-1 00-11 Bits Range Description Reloads the register bit values into the device Initializes all register bit values to zero (default setting) Cycles through ACLK frequencies (Table 3) Bit 3 enables or disables offspeed mode; Bit 4 adjusts ACLK off-speed high or low Cycles through UCLK frequencies (Table 5) Switches the CLK27 output between the VCXO and UCLK frequency Digital Coarse tune adjustment of the VCXO Enables fine tune of the VCXO via the XTUNE pin Cycles through PCLK frequencies via PSEL0 and PSEL1 pins (Table 6) Exits the demo program Figure 6: Board Silkscreen Figure 7: Board Traces - Component Side VCXO VCXO Enable PCLK Exit V E P X 9-12 13 - Left Right Table 19: Cable Interface Color Red White Green Blue Brown Black J1 1 2 3 4 5 6 DB25 2 16 8 5 4 25 Signal SCLK SDATA SLOAD PSEL1 PSEL0 GND Figure 8: Board Traces - Solder Side Right Left ,62 15 7.20.98 |
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